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E2A0024-16-X1 Semiconductor
Semiconductor MSM7524
DTMF Transceiver
This version: Jan. 1998 MSM7524 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7524 is the single chip DTMF transceiver -generator/receiver- with the call progress tone generator/detector and the special tone -1300 Hz in the first version, possible to be modified- detector. Each function block can be controlled by an external MCU via 4-bit processor interface. The chip operates with +5 V single supply with low power consumption, and is suitable for the telephone terminal equipment.
FEATURES
* Power supply voltage : +5 V 10% * Low power consumption Operating mode : 8 mA Typ. Power down mode : 10 mA Typ. * 4-bit processor interface * Dynamic range of DTMF receiver : 40 dB * Low signal distortion output from DTMF generator * Call progress tone detector : 330 to 640 Hz * Call progress tone generator : 350/400/440/480 Hz * Special tone detector: 1300 Hz 20 Hz (for FAX) * 3.58 MHz crystal oscillator circuit on chip * Package : 32-pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name : MSM7524GS-K)
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Semiconductor
MSM7524
BLOCK DIAGRAM
FXI- (28) GS3 (29) CPI+ (30) CPI- (31) GS2 (32) PBI+ (3) PBI- (2) GS1 (1) PBTO (24) PBA- (25) PBAO (26) CPTO (7) CPA- (6)
- +
OPA-IV
PRE LPF
FX Detector
FX (27)
+ -
OPA-V
PRE LPF
C.P.T* Detector
CP (22)
+ -
OPA-I
PRE LPF
DTMF Receiver
Control Register A&B
- +
LPF OPA-III
DTMF Generator D1 (21) D2 (20) D3 (19) D4 (18) SCLK (14) R/W (17) AD0 (16) CS (15) X1 (11) X2 (12)
- +
C. P. T* Generator OPA-II Status Register
Processor Interface
CPAO (5) SG (4) PON (10) V DD (9) AG (8) DG (23) *C. P. T : Call Progress Tone SG Generator
CLKO (13)
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MSM7524
PIN CONFIGURATION (TOP VIEW)
GS1 PBI- PBI+ SG CPAO CPA- CPTO AG VDD PON X1 X2 CLKO SCLK CS AD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Plastic SSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
GS2 CPI- CPI+ GS3 FXI- FX PBAO PBA- PBTO DG CP D1 D2 D3 D4 R/W
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MSM7524
PIN DESCRIPTION
Pin No. 1 2 3 Name GS1 PBI- PBI+ I/O O I I Description Output and two input pins of the on-chip operational amplifier (1). These pins are used to implement the pre-amplifier for DTMF tone receiving. Refer to Fig. 1.
C1 IN R1
PBI+/CPI+ PBI-/CPIR2 R3 + C1 - GS1/GS2SG IN
R2 PBI-/CPIR3 PBI+/CPI+
GS1/GS2 - SG +
(A)
(B)
* R1, R2, R3 50 kW, C1 = 2.2 F * Voltage Gain; 1 + R2/R3.........(A) R2/R3...............(B) Figure 1 Receive Gain Adjustment Voltage gain should be less than 10(20 dB). DTMF receiver's detect and non-detect amplitude are specified as the receive signal level at GS1. 4 5 6 SG CPAO CPA- O O I On-chip signal ground. The potential is approximately half of VDD. Output and inverting input pins of the on-chip operational amplifier (II). The non-inverting input is internally connected to SG. When not using this amplifier, these pins should be wired to each other. Call progress tone (CPT) output. Tone amplitude is approximately 0 dBm on CPTO, but the transmit signal level can be adjusted by using the on-chip operational amplifier (II). Refer to Fig. 2. Make/Break of CPT transmitting is controlled through the processor interface.
PBTO/CPTO
GENERATOR
7
CPTO
O
R4 PBA/CPA R5 OUT PBAO/CPAO SG - +
* R4, R5, 20 kW * Voltage Gain; R5/R4 10(20 dB) Figure 2 Transmit Gain Adjustment
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MSM7524
Pin No. 8 9
Name AG VDD
I/O -- -- Analog ground, 0 V.
Description This pin should be common with DG (pin 23) at the system ground point. Power supply, +5 V. Power down control. When digital "1" is applied to PON, the whole circuitry on chip falls into the power down mode. This pin is pulled-up to digit "1" internaly. X1 and X2 are connected to a 3.579545 MHz crystal to generate a
10
PON
I
11
X1
I
crystal clock for the chip. If required to use an external clock, X1 should be left open and X2 should be connected to the external clock source via a capacitor of 100 pF. 3.579545 MHz clock output. External processor interface clock input. During "WRITE" mode, the data on D4 to D1 pins are written into the internal register at the falling edge of SCLK. During "READ" mode,
12 13
X2 CLKO
O O
14
SCLK
I
the output data from the internal register appears on D4 to D1 pins at the rising edge of SCLK. SCLK is not required to be a periodic clock pulse stream. SCLK is internally pulled-down to digital "0". Chip select.
15
CS
I
When CS is on digital "0", "READ" and "WRITE" operations become possible. CS is internally pulled-down. Address data input. When digital "1" is applied to AD0, data writing into the control register and data reading out from the status register become possible. When digital "0" is applied to, data writing into the DTMF tone transmit register and data reading out from the DTMF tone receive register become possible. AD0 is internally pulled-down. "READ" and "WRITE" control signal input. "READ" or "WRITE" operation becomes possible during digital "1" or "0", respectively. R/W is internally pulled-down to digital "0".
16
ADO
I
17
R/W
I
18 19 20 21
D4 D3 D2 D1
I/O I/O I/O I/O 4-bit micro-processor interface bus. All pins are internally pulled-down.
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MSM7524
Pin No.
Name
I/O Call progress tone detect.
Description When the tone is detected, CP shows digital "1" state. Detected call progress
22
CP
O
tone frequency and amplitude range are specified as follows. Frequency; 330 to 640 Hz Amplitude; 0 to -40 dBm (at GS2) Digital ground, 0 V. This pin should be common with AG (pin 8) at the system ground point. DTMF tone output. The signal amplitude of the low-group and the high-group tones are -6.5 dBm and -5.5 dBm at PBTO, respectively, but, the transmit signal
23
DG
--
24
PBTO
O
amplitude can be adjusted by applying the on-chip operational amplifier (III). Refer to Fig. 2. Make/Break of DTMF tone transmitting is controlled through the processor interface. Inverting input and output pins of the on-chip operational amplifier (III). The non-inverting input is internally connected to SG. When not using this amplifier, these pins should be wired to each other. Special tone detect. The MSM7524 first version provides this function for 1300 Hz tone which is well-known for FAX auto-receipt. When the tone is detected, FX shows digital "1" state. Detected tone frequency and amplitude range are specified as follows. Frequency: 1280 to 1320 Hz Amplitude: 0 to -34 dBm (at GS3) When CP is on digital "1" (call progress tone is detected), FX is forced to be on digital "0" state regardless of the special tone existence.
25 26
PBA- PBAO
I O
27
FX
O
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MSM7524
Pin No.
Name
I/O
Description Special tone input and gain adjustment. FXI- and GS3 are connected to the inverting input and the output of the on-chip operational amplifiers (IV). The inverting input of the amplifier (IV) is internally connected to SG. When not using the special tone detect function, FXI- and GS3 should be wired to each other. Regarding the gain adjustment, refer to Fig. 3.
C1 IN R3 GS3 SG R2 FXI- +
28
FXI-
I
29
GS3
O * R2, R3, 50 kW, C1 = 2.2 F * Voltage Gain; R3/R2 10 (20 dB) Figure 3 Receive Gain Adjustment for FX Two input and output pins of the on-chip operational amplifier (V).
30
CPI+
I
These pins are useful to implement the pre-amplifier for Call Progress Tone receiving. Refer to Fig. 1. Voltage gain should be less than 10 (20 dB). Detect and non-detect amplitude are specified as the receive signal level at GS2.
31
CPI-
I
32
GS2
O
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MSM7524
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Condition Ta = 25C With respect to AG or DG -- Rating -0.3 to +7 0.3 to VDD + 0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input Clock Frequency Bypass Capacitor Digital Input Rise Time Digital Input Fall Time Frequency Deviation
Crystal
Symbol VDD Top fCLK VDD SG CVA CSA tlr tlf -- -- -- --
Condition -- -- External Clock Between VDD and AG Between SG and AG CS, AD0, R/W, D4 to D1, PON, SCLK +25C 5C At -25C to 85C -- --
Min. +4.5 -25 -0.1 0.1 + 10 1 -- -- -100 -50 -- --
Typ. +5.0 -- -- -- -- -- -- -- -- -- 16
Max. +5.5 +85 +0.1 -- -- 50 50 +100 +50 50 --
Unit V C % mF mF ns ns ppm ppm W pF
Temperature Characteristics Equivalent Series Resistance Load Capacitance
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ELECTRICAL CHARACTERISTICS
DC and Digital Inerface Characteristics
(VDD = +5 V 10%, Ta = -25C to 85C) Parameter Power Supply Voltage Input Voltage Symbol IDD1 IDD2 VIH VIL IIH Input Leakage Current IIL VOH VOL VOFF RIN VI = 0V -- VI = 5V Condition Operating Mode Power Down Mode -- SCLK, CS, AD0, R/W, D1 to D4 PON SCLK, CS, AD0, R/W, D1 to D4 PON IOH = -0.4 mA IOL = 1.6 mA CPAO, PBAO CPI+, CPI-, PBI+, Analog Input Resistance PBI-, FXI-, PBA-, CPAPBTO, PBAO, Analog Output Resistance ROUT CPTO, CPAO, GS1, GS2, GS3 20 -- -- MW -- 10 -- MW Min. -- -- 2.2 0.0 -10 -10 -10 -80 2.4 0.0 -100 Typ. 8.0 10 -- -- -- -- -- -- -- 0.2 -- Max. 11.0 100 VDD 0.8 +80 +10 +10 +10 VDD 0.4 +100 V V mV mA Unit mA mA V V mA
Output Voltage Analog Output Offset Voltage
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MSM7524
ANALOG INTERFACE CHARACTERISTICS
DTMF Generator
Parameter DTMF Tone Transmit Amplitude Tone Transmit Amplitude Ratio Tone Frequency Accuracy Total Harmonic Distortion Symbol VPBTL VPBTH VPBDF fDPB THDPB at PBTO Condition Low Group Tone High Group Tone VPBTH-VPBTL To Nominal Rrequency Total Harmonics - Fundamental 4 to 8 kHz Out-of-Band Spurious * VSPS 8 to 12 kHz 12 kHz to
(VDD = +5 V 10%, Ta = -25C to 85C) Min. -8.5 -7.5 0.0 -- -- -- -- -- Typ. -6.5 -5.5 1.0 -- -- -- -- -- Max. -4.5 -3.5 2.0 1.5 -23 P-20 P-60 P-60 Unit dBm dBm dB % dB dB dB dB
*P: Inband energy
Call Progress Tone (CPT) Generator
(VDD = +5 V 10%, Ta = -25C to 85C) Parameter Tone Amplitude Symbol VCPT fCPT0 Tone Transmit Amplitude Ratio fCPT1 fCPT2 fCPT3 Tone Harmonic Distortion THDCPT -- at CPTO Condition -- CPT2 = 0, CPT1 = 0 CPT2 = 0, CPT1 = 1 CPT2 = 1, CPT1 = 0 CPT2 = 1, CPT1 = 1 Total Harmonics - Fundamental Min. -2.0 380 330 420 460 -- Typ. 0 400 350 440 480 -- Max. 2.0 420 370 460 500 -23 Unit dBm Hz Hz Hz Hz dB
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MSM7524
Call Progress Tone (CPT) Detector
(VDD = +5 V 10%, Ta = -25C to 85C) Parameter Detect Amplitude Non-detect Amplitude Hysteresis of Detect Amplitude Detect Frequency Time to Detect Time to Reject Detect Delay Time Detect Hold Time Non-detect Frequency Symbol VDETCP VREJCP VHYSCP fDETCP tDETCP tREJCP tDELCP tHOLCP fREJCP Condition fIN: 330 to 640 Hz, at GS2 -- -- Detect Non-detect Refer to Fig. 4. -- Min. -40 -- -- 330 70 -- 35 -- 700 -- Typ. -- -- 4.0 -- -- -- 50 50 -- -- Max. 0 -60 -- 640 -- 35 70 -- -- 270 Unit dBm dBm dB Hz ms ms ms ms Hz
tREJCP
CPI
tDETCP
tDELCP
CP
tHOLCP
Figure 4 CPT Detect Timing
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MSM7524
Special Tone (ex. F-tone for FAX auto-receipt) Detector
(VDD = +5 V 10%, Ta = -25C to 85C) Parameter Detect Amplitude Non-detect Amplitude Hysteresis of Detect Amplitude Detect Frequency Time to Detect Time to Reject Detect Delay Time Detect Hold Time Non-detect Frequency Symbol VDETFX VREJFX VHYSFX fDETFX tDETFX tREJFX tDELFX tHOLFX fREJFX Condition fIN : 1,300 Hz 20 Hz, at GS3 -- -- Detect Non-detect Refer to Fig. 5. -- Min. -34 -- -- 1,280 70 -- 35 -- 1360 -- Typ. -- -- 4.0 -- -- -- 50 50 -- -- Max. 0 -60 -- 1,320 -- 35 70 -- -- 1240 Unit dBm dBm dB Hz ms ms ms ms Hz
tREJFX
FXI
tDETFX
tDELFX
FX
tHOLFX
Figure 5 Special Tone Detect Timing
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MSM7524
DTMF Receiver
(VDD = +5 V 10%, Ta = -25C to 85C) Parameter Detect Amplitude Non-detect Amplitude Detect Frequency Non-detect Frequency Level Twist Noise to Signal Ratio (N/S) Dial Tone Rejection Ratio Signal Repetition Time Time to Detect Time to Reject Interdigit Pause Acceptable Drop Out Detect Delay Time Detect Hold Time Symbol VDETDT VREJDT fDETDT fREJDT VTWIST VN/S VREJ tCYCDT tDETDT tREJFDT tPAUDT tBRKDT tDELDT tHOLDT Refer to Fig. 6. Detect Non-detect Condition fIN : Nominal Frequency 1.5%, at GS1 To Nominal Frequency VHigh Group-VLow Group N : 0.3 to 3.4 kHz 350 to 480 Hz Min. -40 -- -- 3.8 -6.0 -- 22 120 49 -- 30 -- 24 21 Typ. -- -- -- -- -- -12 -- -- -- -- -- -- 41 28 Max. 0 -60 1.5 -- +6.0 -- -- -- -- 24 -- 2 49 35 ms Unit dBm dBm % % dB dB dB
tREJDT
PBI
tCYCDT tDETDT tPAUDT
tBRKDT
tDELDT
D4 to D1 SP
tHOLDT
Figure 6 DTMF Receiver Timing
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MSM7524
Processor Interface Characteristics
(VDD = +5 V 10%, Ta = -25C to 85C) Parameter SCLK Period SCLK Pulse Width AD0 CS R/W D4 to D1 (Write) D4 to D1 (Read) Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Delay Time Hold Time Symbol tCYC tHI tLO tAS tAH tCS tCH tRWS tRWH tDWS tDWH tDRD tDRH Condition Refer to Fig. 7. Digital "1" Digital "0" AD0 AE SCLK SCLK AE AD0 CS AE SCLK SCLK AE CS R/W AE SCLK SCLK AE R/W D4 to D1 AE SCLK SCLK AE D4 to D1 SCLK AE D4 to D1 D4 to D1 AE SCLK Min. 1 400 400 80 10 80 10 80 10 80 10 -- 10 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 150 -- ns Unit
tCYC tHI
SCLK
tLO tAH tCH tRWH tDWH
DATA
tAS
ADO
tAS tCS tRWS tDRD
DATA "READ"
tAH tCH tRWH tDRH
tCS
CS
tRWS
R/W
tDWS
D4 to D1
"WRITE"
Figure 7 Processor Interface READ/WRITE Timing
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MSM7524
PROCESSOR INTERFACE
Internal Register Address and Function Table-1
AD0 0 0 1 1 R/W 0 1 0 1 READ/WRITE WRITE READ WRITE READ Registers DTMF Tone Transmit Data DTMF Tone Receive Data Control Data Status Data
DTMF Tone Transmit/Receive Data Registers Table-2
D4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D 697 770 852 941 1633 941 852 770 697 Low-Group Tone (Hz) High-Group Tone (Hz) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477
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MSM7524
Control Data Register A Table-3-1
D4 RSEL D3 -- D2 CPEN D1 MFC
Table-3-2
Bit Name Control data register select. "0" : Register A is selected. D4 RSEL "1" : Register B is selected on the next Write cycle to the Control Register address. Subsequent Write cycles to the Control Register are directed back to Control Register A. D3 D2 -- CPEN Not used. Set to digital "0" or "1". Call Progress Tone (CP)/Special tone (FX) detect control. "0" : Disable CP and FX. Both CP and FX are held on digital "0". "1" : Enable CP and FX. DTMF Tone Transmit Make/Break control. D1 MFC "0" : Disable. PBTO outputs only DC potential at SG. "1" : Enable. DTMF tone is generated via PBTO. Function
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MSM7524
Control Data Register B Table-4-1
D4 CPT2 D3 CPT1 D2 CPTC D1 --
Table-4-2
Bit Name Call Progress tone frequency select. CPT2 D4 D3 CPT2 CPT1 0 0 1 1 CPT1 0 1 0 1 Frequency (Hz) 400 350 440 480 Function
Call Progress tone Transmit/Make/Break control. D2 D1 CPTC MFC "0" : Disable. CPTO outputs only DC potential at SG. "1" : Enable. Call Progress tone is generated via CPTO. Not used. Set to digital "0" or "1".
Note) All control data on Registers A and B should be cleared by software and/or PON control. Power-down control by PON makes all logic status and control data to be cleared.
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MSM7524
Status Data Register Table-5-1
D4 SP D3 SPFLG D2 CPFLG D1 AFLG
Table-5-2
Bit D4 Name Signal Present for DTMF tone receive. SP "0" : Valid data is in the receive data register. "1" : Data is invalid. D3 D2 D1 SPFLG CPFLG AFLG Flag for valid DTMF tone receive. SPFLG is reset to digital "0" after an external processor reads out the status register data. Flag for valid Call Progress tone detect. CPFLG is reset to digital "0" after an external processor reads out the status register data. AFLG is set to digital "1" when SPFLG and/or CPFLG is set to digital "1". After an external processor reads out the status register data, AFLG is reset to digital "0". Function
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MSM7524
PROCESSOR CONTROL
Table-6 An example of the micro-processor control for each mode is shown in Table-6.
Mode q Power ON w Processor Control Clear CRA. (CRB is selected next.) Clear CRB. (CRA is selected next.) Observe STR. (Non detect state) Observe STR. (Detect state) Observe STR. (Detect state or After read STR) Observe STR. (For next tone) Observe STR. (Non detect state) Observe STR. (Detect state) Observe STR*. (Detect state or After read STR) DTMF tone transmit "Make". DTMF tone transmit "Break". CPT transmit ON. CPT transmit OFF. Transmit "Make" Transmit "Break" CS AD0 R/W D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 0 X 1 0 0 X 1 0 1 1 1 X 0 0 1 X 1 X D3 0 0 X 0 1 0 X 0 -- 0 0 0 X -- -- -- X -- X D2 0 0 X 0 0 0 X 0 1 0 1 0 X 0 0 0 1 0 0 D1 0 0 X 0 1 0 X 0 0 0 1 0 X 1 0 0 -- 0 -- Valid Register CRA CRB CRA STR STR STR RR STR CRA STR STR STR TR CRA CRA CRA CRB CRA CRB
e Next mode is selected. q w DTMF Tone Receive e
r Read RR. t
q CPT detect enable. w CPT Detect e r
q DTMF tone data. DTMF Tone Transmit e w
q Select CRB. CPT Transmit w
e Select CRB. r
* CP is still held on digital "1" while CPT is detected. Note) CPT : CRA : CRB : STR : Call Progress Tone Control Resister A Control Register B Status Register TR RR X -- : : : : DTMF Tone Transmit Register DTMF Tone Receive Register Expected Data Digital " 0" or "1" 19/21
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MSM7524
APPLICATION CIRCUIT
MSM7524 R1 DTMF Tone Analog Input C1 R2 1 GS1 2 PBI3 PBI+ 4 SG C4 5 CPA0 6 CPACPT Output (Load 50 kW)
32 R3 GS2 31 CPI30 CPI+ GS3 FXI27 FX 26 CPT0 PBA0 25 AG PBA24 VDD PBT0 23 DG 22 X1 CP 21 X2 CLK0 SCLK D1 20 D2 19 D3 18 D4 17 AD0 R/W To MPU CS PON
DTMF Tone (Load 50 kW)
R4
C2
CPT Analog Input
29 R5 28
SG R6 C3 Special Tone Analog Input
7 8 - + C5 9 10 11 12
0V C6 +5 V
Crystal 13 3.579545 MHZ
14 15 16
R1 to R6 50 kW, C1, C2, C3 = 0.22 F, C4, C5 = 1 F, C6 = 10 F DTMF Tone : Receive Gain CPT Detect : Gain Special Tone : Detect Gain R1/R2 R3/R4 R5/R6 *R1 = R2 = 50 kW, Receive Range : -40 to 0 dBm *R3 = R4 = 50 kW, Detect Range : -40 to 0 dBm *R5 = 100 kW, Detect Range : -40 to 6 dBm R6 = 50 kW
Note) The decoupling capacitors (C4, C5, C6) should be connected close to the device. 20/21
Semiconductor
MSM7524
PACKAGE DIMENSIONS
(Unit : mm)
SSOP32-P-430-1.00-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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